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MC74HC393A Dual 4-Stage Binary Ripple Counter
High-Performance Silicon-Gate CMOS
The MC74HC393A is identical in pinout to the LS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two independent 4-bit binary ripple counters with parallel outputs from each counter stage. A / 256 counter can be obtained by cascading the two binary counters. Internal flip-flops are triggered by high-to-low transitions of the clock input. Reset for the counters is asynchronous and active-high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the HC393A.
http://onsemi.com MARKING DIAGRAMS
14 PDIP-14 N SUFFIX CASE 646 MC74HC393AN AWLYYWW 1 14 SOIC-14 D SUFFIX CASE 751A 1 14 TSSOP-14 DT SUFFIX CASE 948G HC 393A ALYW HC393A AWLYWW
* * * * * * *
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 236 FETs or 59 Equivalent Gates
LOGIC DIAGRAM
1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
PIN ASSIGNMENT
3, 11 CLOCK 1, 13 4, 10 BINARY COUNTER 5, 9 6, 8 2, 12 PIN 14 = VCC PIN 7 = GND Q1 Q2 Q3 Q4 CLOCK a RESET a Q1a Q2a RESET Q3a Q4a GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC CLOCK b RESET b Q1b Q2b Q3b Q4b
FUNCTION TABLE
Inputs Clock X H L Reset H L L L L Outputs L No Change No Change No Change Advance to Next State
ORDERING INFORMATION
Device MC74HC393AN MC74HC393AD MC74HC393ADR2 MC74HC393ADT MC74HC393ADTR2 Package PDIP-14 SOIC-14 SOIC-14 TSSOP-14 TSSOP-14 Shipping 2000 / Box 55 / Rail 2500 / Reel 96 / Rail 2500 / Reel
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 2
Publication Order Number: MC74HC393A/D
MC74HC393A
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MAXIMUM RATINGS*
SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC
- 55 0 0 0 0
+ 125 1000 600 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.80 1.9 4.4 5.9
v 85_C v 125_C
1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.80 1.9 4.4 5.9 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.80 1.9 4.4 5.9
Unit V
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v v
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
V
VOH
Minimum High-Level Output Voltage
Vin = VIH or VIL |Iout| 20 A
v
V
Vin = VIH or VIL |Iout| |Iout| |Iout|
v 2.4 mA v 4.0 mA v 5.2 mA
2.48 3.98 5.48
2.34 3.84 5.34
2.20 3.70 5.20
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NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Symbol
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tTLH, tTHL
VOL
tPHL
fmax
ICC
Cin
Iin
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Maximum Input Capacitance
Maximum Output Transition Time, Any Output (Figures 1 and 3)
Maximum Propagation Delay, Reset to any Q (Figures 2 and 3)
Maximum Propagation Delay, Clock to Q4 (Figures 1 and 3)
Maximum Propagation Delay, Clock to Q3 (Figures 1 and 3)
Maximum Propagation Delay, Clock to Q2 (Figures 1 and 3)
Maximum Propagation Delay, Clock to Q1 (Figures 1 and 3)
Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 3)
Parameter
Parameter
Vin = VIH or VIL |Iout| 20 A
Vin = VCC or GND Iout = 0 A
Vin = VCC or GND
Vin = VIH or VIL |Iout| |Iout| |Iout|
v
Test Conditions
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MC74HC393A
3
v 2.4 mA v 4.0 mA v 5.2 mA
VCC V
VCC V
2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 6.0 3.0 4.5 6.0 2.0 4.5 6.0
--
- 55 to 25_C
- 55 to 25_C
0.1
0.26 0.26 0.26
160 110 52 44
130 80 44 37
100 56 34 20
0.1 0.1 0.1
10 75 27 15 13 80 48 30 26 70 40 24 20 10 15 30 50 4
Guaranteed Limit
Guaranteed Limit
v 85_C v 125_C
v 85_C v 125_C
1.0
0.33 0.33 0.33
250 185 65 55
150 105 55 47
105 70 45 38
0.1 0.1 0.1
9 14 28 45
10 95 32 19 16 95 65 38 33 80 45 30 26 40
1.0
0.40 0.40 0.40
300 210 82 65
180 130 70 58
180 100 55 48
160
110 36 22 19 110 75 50 43 0.1 0.1 0.1 8 12 25 40 90 50 36 31
10
MHz
Unit
Unit
A
A
pF ns ns ns ns ns ns V
MC74HC393A
Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Counter)* 35 pF * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I
Guaranteed Limit Symbol trec Parameter VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 25 15 10 9 75 27 15 13 75 27 15 13
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
v 85_C v 125_C
30 20 13 11 95 32 19 15 95 32 19 15 40 30 15 13
Unit ns
Minimum Recovery Time, Reset Inactive to Clock (Figure 2)
tw
Minimum Pulse Width, Clock (Figure 1)
110 36 22 19 110 36 22 19
ns
tw
Minimum Pulse Width, Reset (Figure 2)
ns
tr, tf
Maximum Input Rise and Fall Times (Figure 1)
1000 800 500 400
1000 800 500 400
1000 800 500 400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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MC74HC393A
PIN DESCRIPTIONS
INPUTS Clock (Pins 1, 13) OUTPUTS Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)
Clock input. The internal flip-flops are toggled and the counter state advances on high-to-low transitions of the clock input.
CONTROL INPUTS Reset (Pins 2, 12)
Parallel binary outputs Q4 is the most significant bit.
Active-high, asynchronous reset. A separate reset is provided for each counter. A high at the Reset input prevents counting and forces all four outputs low. SWITCHING WAVEFORMS
tf 90% 50% 10% tw 1/fmax tPLH tPHL Q 90% 50% 10% CLOCK tTLH tTHL Q tr VCC RESET GND tPHL 50% trec VCC 50% GND 50% GND tw VCC
CLOCK
Figure 1.
Figure 2. EXPANDED LOGIC DIAGRAM
CLOCK 1, 13 D CL* C Q Q 4, 10 Q2 C Q Q 3, 11 Q1
TEST POINT OUTPUT DEVICE UNDER TEST
*Includes all probe and jig capacitance
D
Figure 3. Test Circuit
C D Q Q 5, 9 Q3
C D
Q Q 6, 8 Q4
RESET
2, 12
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MC74HC393A
TIMING DIAGRAM
0 CLOCK RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
Q1 Q2 Q3 Q4
COUNT SEQUENCE
Outputs Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q4 L L L L L L L L H H H H H H H H Q3 L L L L H H H H L L L L H H H H Q2 L L H H L L H H L L H H L L H H Q1 L H L H L H L H L H L H L H L H
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MC74HC393A
PACKAGE DIMENSIONS
PDIP-14 N SUFFIX CASE 646-06 ISSUE L
14 8
B
1 7
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01
A F C N H G D
SEATING PLANE
L
J K M
SOIC-14 D SUFFIX CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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MC74HC393A
PACKAGE DIMENSIONS
TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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EE CC EE CC
A -V-
MC74HC393A/D

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